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EUV lithography machine battle, sudden change in situation

2025-02-01

EUV lithography machine battle, sudden change in situation

Observation of the Semiconductor Industry

This article is from WeChat official account: Semiconductor Industry Watch (ID: icbank), written by L Chenguang, and the title is from AI Generation


Starting from early deep ultraviolet (DUV) lithography machines, their stable and reliable performance laid a solid foundation for the development of the semiconductor industry; Later on, extreme ultraviolet (EUV) lithography machines, with their unique extreme ultraviolet light source and shorter wavelength, successfully pushed lithography accuracy to new heights; Nowadays, the High NA lithography machine has officially entered the historical stage, further improving the accuracy and efficiency of lithography, providing the possibility for manufacturing smaller and more precise chips.


Especially with the advent of the ASML High NA EUV lithography machine, which is currently the world's most advanced chip manufacturing equipment, the transistor density and performance of chips have been significantly improved, which is crucial for achieving large-scale production of advanced processes below 2nm.


In this situation, major wafer manufacturers such as Intel, TSMC, Samsung, and SK Hynix are waiting for the opportunity to introduce or announce the progress of the High NA EUV lithography machine market, indicating that the semiconductor industry will usher in a new round of technological innovation and competition.


1、 Intel: Misfortune


Among semiconductor giants, Intel was the first to order the new High NA EUV equipment EXE: 5000 from ASML.


As early as December 2023, Intel acquired the world's first High NA EUV lithography machine and announced in April this year that it had completed the assembly of the world's first commercial High NA (0.55NA) EUV lithography machine at its Fab D1X R&D wafer fab in Hillsborough, Oregon, USA. It has now entered the optical system calibration phase and plans to use it on its 18A (1.8nm) and 14A (1.4nm) nodes.


In August of this year, Intel announced the successful receipt of the world's second High NA EUV lithography machine worth $383 million, which has been successfully installed and debugged at its wafer fab in Oregon.


ASML had previously stated that the current production capacity of 2nm lithography machines is only 10 units, and it is expected to produce 20 units per year by 2028. It is worth noting that among these 10 latest lithography equipment, public information shows that 6 have been acquired by Intel.


It can be seen that Intel has achieved a leading advantage in the import progress of the most advanced lithography machines.


As the saying goes, 'Learn from a setback, gain wisdom.' The reason why Intel is so actively choosing High NA EUV equipment is actually largely due to its previous decline in EUV technology.


1. Tick Lock mode collapses and misses the EUV technology window


As is well known, Intel has been cooperating with ASML for decades, promoting the development of lithography technology from 193nm immersion lithography to EUV. However, due to cost considerations, the then CEO of Intel was unwilling to use the expensive ASML EUV lithography machine and chose not to use this technology in its 10nm process, but instead used a DUV lithography machine for quadruple patterning. As a result, Intel encountered numerous difficulties in yield.


Looking back at history, it can be seen that in 2011, Intel launched the 22nm FinFET process, far surpassing TSMC and Samsung's 28nm at the time, and its technological advantage can be said to be far ahead. However, starting from the 14nm node, Intel suffered consecutive heavy losses.


In 2014, both Intel and Samsung achieved the production of 14nm process chips, but by 2017, TSMC had advanced to 10nm and 7nm processes. However, Intel was unwilling to adopt the latest EUV lithography technology, which led to its original plan to mass produce 10nm chips in 2016 until 2019, two and a half years later than TSMC's launch time. Its 7nm chips were not launched until 2022.


In fact, apart from failing to grasp EUV technology, the decline of Intel's foundry industry is also closely related to its "Tick Lock" strategy.




Former Intel CEO Paul Otellini proposed the "Tick Lock" strategy for chip manufacturing, which involves updating manufacturing processes in Tick year (process year) and microarchitecture in Tock year (architecture year), equivalent to making process progress every two years. However, during the same period, in order to implement "efficient management" and "cost saving plans", Intel laid off 20000 employees, and a large number of engineers involved in the research and development of next-generation chip processes and architectures were laid off, making it difficult to sustain the "Tick Lock" mode. The launch of 14nm chips was delayed by one year, and 10nm chips were delayed several times.




Intel made small annual updates to chip technology like squeezing toothpaste, and in those years it was once ridiculed as a "toothpaste factory".




With the collapse of Tick Lock mode and missing out on the early EUV technology window, Intel is gradually falling behind.




At the same time, TSMC and Samsung have purchased EUV equipment in large quantities from ASML, continuously reducing the process size of chips, improving their efficiency and performance, and greatly enhancing their competitiveness in the field of wafer foundry. Intel is far behind TSMC and Samsung in advanced manufacturing processes.




More seriously, outdated production processes and declining product competitiveness not only affect Intel's OEM business, but also continuously erode its market share in desktop and server chips.




It can be said that one pull can move the whole body.




2、 Intel saves itself, where is the way forward?




Therefore, after learning from the pain, Intel took the lead in launching an attack on the High NA EUV lithography machine, attempting to catch up with the gap that had been widened.




As mentioned above, in April 2024, a massive equipment weighing 150 tons was installed at Intel's research facility in Oregon, USA.




After Intel CEO Pat Gelsinger proposed the "IDM 2.0" strategy, he quickly refocused on improving cutting-edge process technology and proposed a plan of four years and five process nodes, hoping to catch up and surpass TSMC's 2nm process with Intel 18A by 2025.








At the same time, Intel hopes to achieve sustained leadership over competitors such as TSMC by being the first to adopt High NA EUV lithography machines. Intel's goal is to achieve mass production of Intel 14A process technology between 2026 and 2027, and further enhance process technology based on this. By 2030, we aim to achieve a balanced operating profit margin for Intel's foundry business and become the world's second-largest wafer foundry.




Guided by its goals, Intel is continuously strengthening its foundry infrastructure and plans to invest $100 billion over the next five years to expand its advanced chip manufacturing capabilities. At the same time, approximately 30 billion euros will be invested to build two semiconductor factories in Magdeburg, Germany. These investment plans will significantly enhance Intel's chip foundry capabilities.




However, the strategic vision is beautiful, but the reality is cruel.




Despite Intel's ambitious goals, due to significant investments in four years, five milestones, route evolution, ecosystem building, and capacity expansion, Intel disclosed that its foundry business revenue decreased by 31.2% year-on-year to $18.9 billion last year, with an operating loss of $7 billion, an increase of 34.6% year-on-year.




2024 is likely to be the year with the most severe operating losses for Intel's chip manufacturing business. This year's Q1 financial report shows that the business is operating at a loss of $2.5 billion, almost twice that of the previous quarter; The Q2 loss reached 2.83 billion US dollars, and the OEM loss continued to expand.




According to research firm TrendForce, Intel did not make it into the top 10 global wafer foundries in terms of revenue in the second quarter of 2024. In the past few years, Intel briefly made the list in the third quarter of 2023, with a market share of only 1%.




This means that IFS has not been able to truly support Intel's goal of reshaping its industry position with cutting-edge chip manufacturing in the past three years, and as the only domestic company in the United States capable of taking on the role of cutting-edge foundry industry, Intel is also unable to shoulder the responsibility of the times.




According to Mind Watch, Jay Goldberg, President of D2D Advisory, a US semiconductor consulting firm, specifically pointed out that "the real challenge facing Intel's foundry industry is that they must have more customers in their economic model to support the research and development needed to continuously advance their manufacturing processes. They must increase external customer demand and double their revenue scale to support continuing to move forward on the track of Moore's Law




It is not difficult to see that Intel is currently in a dilemma, with its performance continuing to decline. In 2024, it may even turn from profit to loss, with its stock price plummeting by nearly 60% and its market value falling below $100 billion several times, making it one of the worst performing technology stocks in the S&P 500 index.




Faced with the crisis, Intel stated in an internal letter that it will further separate its chip manufacturing and design businesses, as part of a series of new measures to address one of the most severe crises in its 50 year history.




According to Intel's previously released forecast data, the spin off of wafer manufacturing business can save $3 billion in costs by 2023 and $8-10 billion in costs by 2025. At the same time, the plans to build factories in Germany and Poland have been postponed for 2 years; The construction of the factory in Malaysia will be completed, but the official opening time will depend on market conditions and capacity utilization.




While Intel continues to urgently execute the plan announced last month, it is also working to prudently manage its existing cash to meaningfully improve its balance sheet and liquidity. This includes selling a portion of Altera's shares and promoting its independent IPO; In terms of product development strategy, we also plan to simplify the x86 product portfolio. This is also a plan that Intel has publicly discussed multiple times.




In August of this year, it was even revealed that Intel was considering splitting its products and outsourcing business. It is worth mentioning that after rumors or spin offs of its wafer business, Intel's stock price rebounded by more than 9%, indicating how disappointed investors are with its chip foundry business.




Intel, which is in a low point, is a microcosm of the US chip manufacturing industry. Costs, technology, resources, IDM identity, and other factors are all constraining Intel's ambitious chip foundry plans. However, despite the possibility of abandoning chip outsourcing in the industry and the continuous losses in the chip outsourcing business that have dissatisfied the capital market, this is also one of the few key layouts that can save Intel from fire and water.




Intel has no choice but to seize any possibility and grit its teeth.




Therefore, Intel needs the most advanced High NA EUV lithography machine as a production and marketing tool to demonstrate its R&D and manufacturing capabilities below 3nm and attempt to expand its customer base. However, as a new machine, the High NA EUV lithography machine has forced Intel to bear the pressure of equipment depreciation and production amortization costs to quell external doubts.




From the sustained competition in the industry and the "heavy asset, long cycle" nature of chip manufacturing, Intel still has many tough battles to fight. Especially in the context of Intel embarking on the largest transformation in company history to save itself.




Intel has also had experiences of recovering from difficulties in the past. In the 1980s, under the attack of Japanese companies, Intel withdrew from DRAM and focused its operating resources on CPUs, sweeping the personal computer market.




As Kissinger said, "This is Intel's most important transformation in over forty years. We haven't tried anything so important since transitioning from memory to microprocessors. We succeeded at the time, and we will embrace this moment and build a stronger Intel in the coming decades




But Intel's various self-help measures still need time to be tested.




3、 Samsung Electronics, shrouded in the shadow of OEM manufacturing




In August of this year, at the "2024 Lithography+Pattern Academic Conference", Samsung Electronics stated that in order to maintain competitiveness in the "chip war" with global semiconductor competitors such as Intel and TSMC, the company is actively participating in technology development. The company will introduce its first High NA EUV equipment "EXE: 5000" between the end of 2024 and the first quarter of 2025, and is expected to achieve full commercialization of this technology by 2027.




It is reported that the device may be placed at the Semiconductor Research Institute (NRD) located in the Huacheng Park, and is expected to be used for foundry business to further enhance its competitive advantage in the advanced node field.




In fact, Samsung chip foundry had an absolute advantage in the early years. When Steve Jobs released the first generation iPhone in 2007, he used ARM architecture chips purchased from Samsung. The A4, A5, A6, and A7 chips that were later installed on the iPhone 4, iPhone 4s, iPhone 5, and iPhone 5s/5c were all manufactured by Samsung, and at that time there was no TSMC involved.




Until 2011, Samsung had a competitive relationship with Apple in the smartphone market because it was also engaged in the research and sales of mobile phone chips and terminals. Both sides struggled with each other until a settlement was reached in June 2018.




During this process, Apple also initiated the process of "de Samsung". The A8 chip launched in 2014 was entirely manufactured by TSMC. TSMC successfully snatched Apple's order from Samsung, partly because Apple was eager to find alternative contract manufacturers, creating great opportunities for TSMC. On the other hand, TSMC has made significant breakthroughs in the 20nm process, resulting in a significant increase in yield rate. However, Samsung's 20nm process suddenly fell short, and the key issue has been unresolved, with yield rate not meeting Apple's requirements. It is precisely this favorable timing and location that has enabled TSMC to successfully hold onto the thigh of Apple.




On the other hand, Samsung, after its major clients were robbed, decided not to pursue 20nm and chose to directly jump from 28nm to 14nm, which formed a backlash against TSMC's 16nm. So, in the 2015 A9 chip, Apple redistributed some orders to Samsung, resulting in two versions: TSMC OEM and Samsung OEM. In theory, Samsung's 14nm performance should be better than TSMC's 16nm, but consumers' reputation is completely opposite, and many people are worried about buying Samsung's OEM version.




This defeat has caused Samsung to completely lose Apple's OEM orders. Apple's subsequent chips are all manufactured by TSMC, and the manufacturing process has steadily increased from 16nm in 2015 to 4nm.




At the same time, Qualcomm almost fell behind in Samsung's OEM, and Snapdragon 8+Gen1 urgently switched to TSMC's 4nm OEM, which forcibly regained Qualcomm's reputation and market position.




On the chip foundry track, Samsung had a starting advantage, but unfortunately, it was only after multiple consecutive failures in the mid-term that TSMC gradually achieved a comeback and today's significant lead. However, Samsung is also aware of the technological gap between itself and TSMC, so in order to surpass TSMC, it must come up with a stronger "trump card".




So, Samsung almost placed all its hopes of catching up with TSMC on the 3nm process. In 2023, Samsung will be the first to launch a 3nm process technology, using more advanced GAA (Surrounding Gate Transistor) technology, leading TSMC's FinFET technology.




It can be said that 3nm is equivalent to Samsung's final "last ditch battle". If they can catch up with TSMC in one fell swoop, there may be a chance to form a situation of dual dominance in the future.




However, from the perspective of market progress, Samsung's 3nm process faces challenges in yield, which has led to an awkward situation where Samsung's 3nm chips, although launched earlier than TSMC, have much higher costs and performance gaps. It is reported that the yield rate of Samsung's second-generation 3nm process technology is unstable, and the yield rate of their own Exynos 2500 is less than 20%. The Samsung Galaxy 25 series smartphones are all equipped with Snapdragon 8Gen4 processors and have abandoned the self-developed Exynos 2500 version due to significant differences in user experience.




After the gap with TSMC widened, fewer and fewer customers placed orders with Samsung.




In the past, Qualcomm's advanced process chips were exclusively manufactured by Samsung. As a result, after the 5nm chip, Qualcomm also handed over orders for advanced process chips to TSMC; Nowadays, Apple's A17 and A18 series chips are all manufactured using TSMC's 3nm process; Qualcomm's 3nm chips and MediaTek's Dimensity 9400 are all manufactured by TSMC; Even Nvidia, AMD, and Tesla's 3nm chips are manufactured by TSMC, and now Intel's orders have also been given to TSMC.




In chip manufacturing, TSMC alone holds over 60% of the global market share, with almost 100% of the market share in 3nm chip manufacturing and 90% of the market share in chip manufacturing below 7nm. The market share of Samsung, the second largest wafer fab, is only 11.5%.




According to the Chosun Ilbo, Samsung has shut down 30% of its 4nm, 5nm, and 7nm production lines at Plant 2 and Plant 3 in Pyeongtaek. It is expected that by the end of 2024, production capacity will continue to be shut down until 50%. This measure is clearly aimed at addressing the current situation where global tech giants such as NVIDIA, AMD, and Qualcomm have failed to provide Samsung Electronics with large-scale orders.




Industry experts emphasize that once a device is shut down, restoring normal operation is a lengthy process. Usually, even during periods of low demand, companies will lower their utilization rates instead of shutting down completely. However, the fact that nearly 30% of Samsung's advanced process equipment is idle is unprecedented.




In the third quarter of 2024, Samsung's non memory division, including wafer foundry and system LSI, incurred losses exceeding KRW 1 trillion. In addition, the yield of Samsung's 3nm process has remained low and has not been adopted by major customers. Recently, the production time of the advanced foundry wafer factory in Taylor, Texas, has been postponed to 2026.




Overall, this gap has completely shattered Samsung's dream of surpassing TSMC in the 3nm era.




Therefore, the news of Samsung introducing the High NA EUV lithography machine means that it will compete more fiercely with Intel and TSMC in the next generation of lithography technology.




Samsung plans to mass produce 2nm processes by 2025 and gradually expand to other application areas. For example, it will first be used in the field of action in 2025, expanded to HPC applications in 2026, and then expanded to the automotive industry in 2027. Samsung's 2nm process nodes adopt optimized backside power supply network technology to reduce interference from power supply circuits to signal circuits.




This development marks Samsung's first foray into High NA EUV technology. Previously, Samsung Electronics had collaborated with IMEC on circuit processing research. Samsung plans to accelerate the development of advanced nodes using its own devices and has set a goal of commercializing 1.4nm processes by 2027, which may pave the way for 1nm production.




In addition, in order to achieve comprehensive commercialization, Samsung is actively building related ecosystems.




It is reported that Samsung Electronics has purchased Laser Technologies' High NA EUV mask inspection equipment "Actis (ACTIS) A300". It is expected that ASML's EXE: 5000 installation will be completed internally at Samsung Electronics, and it will be officially introduced starting from the first half of next year. Simultaneously collaborating with electronic design automation (EDA) companies to design new photomasks, including a non-linear (Curvilinear) mask circuit drawing method for High NA EUV, to improve the clarity of printed circuits on wafers. This collaboration involves companies such as Synopsys, a global leader in semiconductor EDA tools.




In addition to ASML, Laser Technologies, and Synopsys, Samsung Electronics is expected to collaborate with photoresist companies such as JSR and tracking equipment "Number One" Tokyo Electronics, which applies photoresist onto wafers, to prepare for the arrival of the High NA era. It is reported that Samsung Electronics is preparing to officially commercialize High NA in 2027 through such ecosystem construction work.




Samsung Electronics' wafer foundry business is standing at a critical crossroads, and its survival seems to depend entirely on the mass production of 2nm chip process technology. This is not only a technological leap, but also the key to whether Samsung's wafer foundry business can be revitalized.




However, the path to success is never smooth sailing. In the process of advancing its technological blueprint, Samsung has to face a series of severe challenges:




Firstly, there are technical challenges, and the yield issue of advanced processes has always been a Damocles sword hanging over semiconductor manufacturers. Samsung's 3-nanometer process failed to meet mass production standards due to low yield and questionable reliability, undoubtedly casting a shadow over its wafer foundry business.




Even worse, the market response did not go as Samsung had hoped. Despite Samsung's efforts to enhance its technological capabilities, the reliability and competitiveness of its wafer foundry business are still lacking in the minds of customers. Facing strong competitors such as TSMC, Samsung seems powerless in attracting high-end customers. This market dilemma further exacerbates Samsung's financial pressure. It is estimated that Samsung's wafer foundry business may lose hundreds of billions of Korean won in the third quarter, which is a major test for Samsung's management.




Faced with internal and external troubles, Samsung's senior management had to make a series of difficult decisions.




According to research firm Statista, despite Samsung's efforts to challenge TSMC over the years, Samsung's market share in the OEM manufacturing market has decreased by 8 percentage points in the past five years. In the second quarter of 2024, Samsung held 11.5% of the global OEM market share, while TSMC held 62.3% of the market share.




The decline in Samsung's market share highlights the technological challenges it faces in mastering advanced chip manufacturing technology. It has invested too much in its foundry business, which has resulted in insufficient customer acquisition and unstable production processes, further leading to Samsung's current crisis.




Overall, the semiconductor industry itself is a field of rapid technological iteration and market volatility, and Samsung must maintain sufficient sensitivity to cope with future changes. How to find a suitable path for its own development in the rapidly changing market is an urgent problem that Samsung needs to solve.




4、 TSMC is' orderly 'and wins the' negotiation game '




As a leader in the semiconductor industry, TSMC has made remarkable achievements in the past 30 years. Over the years, facing the enormous challenges and pressures brought by Samsung and Intel, TSMC has assessed the situation and taken effective measures, becoming the world's largest chip foundry enterprise.




Nowadays, even though leading semiconductor companies in the industry are competing for High NA EUV equipment, TSMC seems not eager to join this ranks.




Previously, when it came to when to introduce High NA EUV equipment, Zhang Xiaoqiang, Senior Vice President and Deputy Co Operating Director of TSMC, revealed in an interview with the outside world that TSMC is confident and will not blindly expand its procurement due to competitors' early purchase of equipment. It will still adopt a steady and steady approach to layout advanced processes and meet challenges.




However, recent reports suggest that TSMC is expected to receive the first batch of the world's most advanced chip manufacturing equipment, the High NA EUV lithography machine, from ASML by the end of this year. This news marks another important step for TSMC in the semiconductor manufacturing field.




It is interesting that TSMC initially refused to accept High NA EUV due to cost reasons. Earlier, TSMC CEO Wei Zhe Jia was absent from the "TSMC Technology Seminar 2024" and instead went to ASML headquarters in Eindhoven, Netherlands to discuss equipment.




Now it seems a bit like TSMC's negotiation game, perhaps fighting for better conditions with ASML.




It is rumored that Wei Zhe's family personally negotiated with ASML and reached an agreement to reduce the overall price by nearly 20% by combining the purchase of new equipment and the sale of old models. ASML agreed to sell High NA EUV equipment to TSMC at a discounted price mainly because TSMC is its super VIP customer, and ASML has made significant concessions. This concession includes full assistance to TSMC in machine installation, calibration, and technical support to accelerate the launch timeline.




Therefore, TSMC's attitude has undergone a dramatic change, shifting from hesitating about the price of the new High NA EUV lithography machine to actively seeking cooperation.




It is reported that TSMC is expected to install a new High NA EUV lithography machine in its R&D center near its headquarters in Hsinchu, Taiwan, China, this quarter. In the short term, TSMC plans to primarily use High NA EUV lithography machines for research and development, in order to develop the necessary infrastructure and pattern solutions for customers to drive innovation.




According to ASML's roadmap, the first generation High NA EUV lithography machine TWINSCAN EXE: 5000 may mainly be used by wafer manufacturers for related experiments and testing, so that companies can better understand the use of High NA EUV equipment and gain valuable experience. The actual mass production will depend on the TWINSCAN EXE: 5200 shipped by the end of 2024.








TSMC's upcoming N2 (2 nanometer level) and A16 (1.6 nanometer level) process technologies will rely entirely on traditional EUV equipment, whose optical components have a NA of 0.33. The industry expects TSMC to use 0.55 NA EUV tools in its A14 (1.4 nanometer level) process technology as early as 2028 or later, although the company has not yet officially confirmed this.




Compared with its competitors, TSMC can accumulate valuable experience data and optimize processes through continuous production practice, making it difficult to build a virtuous cycle system of "order driven technology iteration re order". In other words, TSMC has an extremely large group of high-quality customers to assist them in debugging various device bugs, which is exactly what Samsung and Intel lack.




1. TSMC Layout Strategy: No Treasure Left Behind




The author previously mentioned that from the perspective of the layout strategy and approach of the three giants, TSMC is often considered a conservative technology developer who tends to ensure the maturity and reliability of new technologies before deploying them, rather than rushing to bring them to the market.




From the actual market performance, TSMC's move can reduce the risk of technological failure, improve its chip production and quality, and ensure customer satisfaction.




For example, Samsung began using EUV lithography machines in its 7nm process in 2018, but TSMC chose to wait. It was not until the stability and maturity of EUV tools were confirmed, and related issues were resolved or at least identified, that EUV began to be used in the N7+process in 2019.




Since then, in the transition from FinFET to GAA process, TSMC has still re operated this mode. With technological advantages and accumulation in process leadership and production yield, we are fully capable of competing with Samsung, which adopts GAA technology architecture.


TSMC is still slow to invest in BSPDN backside power supply technology, which Intel is heavily betting on, and plans to add it to the N2P, which will not begin mass production until the end of 2026.


This cautious approach helps TSMC ensure the stability and predictability of its process technology, thereby providing high-quality chips to its customers.

However, in the field of advanced packaging, TSMC has changed its usual practice and actively laid out to be the first to land. With the combination of advanced processes and advanced packaging, it has brought a new wave of growth.

Under this balanced strategy, TSMC's strategic philosophy and unique vision are fully highlighted. In the blue ocean track it has set its sights on, TSMC has always dared to take the lead. Whether it was leading the way in trial production of 16nm FinFET process technology ten years ago, surpassing Intel, or deploying advanced packaging five years ago to reap the benefits of AI today, TSMC has brilliantly demonstrated the so-called 'phoenix without treasure'.

In the advanced process field where TSMC maintains a significant advantage, even in the face of the increasing pressure from Samsung and Intel, TSMC did not choose to be blindly aggressive. Instead, it adopted a strategy of observing first and then following suit. After making sufficient preparations and planning, TSMC followed suit step by step, relying on its strong production capacity, yield, and customer base advantages to maintain an unbeatable position.




5、 SK Hynix launches High NA EUV, betting on HBM




In addition, in the storage field, SK Hynix's first High NA EUV lithography machine "EXE: 5200" is expected to be introduced in 2026 to support the mass production of its advanced DRAM products. This measure further demonstrates the semiconductor industry's continuous pursuit and investment in advanced process technology.




In 2023, SK Hynix formed a separate team dedicated to developing High NA EUV technology.




As a giant in the HBM field, SK Hynix is continuously increasing its internal investment in the development of High NA EUV technology and actively expanding its related research and development team. Although the specific wafer fab location and additional investment direction for equipment installation have not been publicly disclosed, the industry generally expects that this technology will be quickly applied to the large-scale production of 0A (single digit nanometer) DRAM to further enhance product competitiveness.

Write at the end

The world below 7nm is a paradise for alternative adventurers, and the competitive relationship between TSMC, Samsung, and Intel has become increasingly subtle.

According to the "Rayleigh formula" of lithography machines, the improvement of lithography processes has been comprehensively advancing in multiple dimensions over the past few decades, continuously optimizing exposure wavelengths, numerical apertures, and process factors. However, the current reduction in exposure wavelength and increase in numerical aperture (NA) have approached the limits of physical and cost considerations.

Nowadays, the limit of Moore's Law is getting closer and closer, and the industry has almost reached the end of the tunnel. 2nm and the next few generations of process nodes will be the key for chip giants to seize the market.

The competition between semiconductor giants such as TSMC, Intel, and Samsung is heating up globally, as they compete to obtain High NA EUV equipment for processes below 2nm. Intel was the first to acquire the device in December 2023, followed closely by TSMC in the third quarter of 2024. Although Samsung's orders came late, achieving stable production may be a key factor in determining its leading position in the industry.


But the competition in chip foundry is not only a competition in technology, but also a comprehensive competition in various aspects such as customers, brands, yield, and production capacity. I don't know if Intel and Samsung can seize the opportunity to rise again in the dawn of the new market. If it fails, TSMC will continue to dominate.






EUV光刻机争夺战,风云突变

本文来自微信公众号:半导体行业观察 (ID:icbank),作者:L晨光,题图来自:AI生成


文章摘要
英特尔、三星、台积电争夺EUV光刻机市场。

•  英特尔积极引入High-NA EUV光刻机,抢占市场先机。

•  三星面临代工业务挑战,力求技术突破。

•  台积电策略稳健,凭借成熟技术保持领先。

光刻机一直是半导体领域的热门话题。


从早期的深紫外(DUV)光刻机起步,其稳定可靠的性能为半导体产业的发展奠定了坚实基础;到后来的极紫外(EUV)光刻机以其独特的极紫外光源和更短的波长,成功将光刻精度推向了新的高度;再到如今的高数值孔径(High-NA)光刻机正式登上历史舞台,进一步提升了光刻的精度和效率,为制造更小、更精密的芯片提供了可能。


尤其是随着ASML High-NA EUV光刻机的问世,这一目前世界上最先进的芯片制造设备,显著提升了芯片的晶体管密度和性能,这对于实现2nm以下先进制程的大规模量产至关重要。


在此形势下,英特尔、台积电、三星、SK海力士等晶圆制造大厂伺机而动,争相导入或宣布High-NA EUV光刻机市场进展,预示着半导体行业将迎来新一轮的技术革新和竞争高潮。


一、英特尔:时运不济


在半导体巨头中,英特尔是率先向ASML订购新型High-NA EUV设备EXE:5000的企业。


早在2023年12月,英特尔就拿下了全球首台High NA EUV光刻机,并于今年4月宣布其已在位于美国俄勒冈州希尔斯伯勒的Fab D1X研发晶圆厂完成世界首台商用High-NA(0.55NA)EUV光刻机的组装工作,目前已进入光学系统校准阶段,并计划在其18A(1.8nm)和14A(1.4nm)节点上使用。


今年8月,英特尔又宣布成功接收全球第二台价值3.83亿美元的High-NA EUV光刻机,目前在俄勒冈州的晶圆厂已经顺利完成安装调试。


ASML早些时候曾表示,2nm光刻机近期的产能只有10台,预计到2028年才能每年生产20台。值得注意的是,这10台最新光刻设备,公开资料显示有6台已被英特尔拿下。


可见,在最先进光刻机的导入进展上,英特尔取得了遥遥领先的优势。


常言道“吃一堑,长一智”,而英特尔之所以如此积极的选择High-NA EUV设备,实际上很大原因在于其此前在EUV上跌过的跟头。


1. Tick-Tock模式溃败、错失EUV技术窗口


众所周知,英特尔与ASML合作了数十年时间,推动了光刻技术从193nm浸没式光刻技术发展到EUV,但出于成本考虑,英特尔时任CEO不愿采用昂贵的ASML EUV光刻机,选择不在其10nm工艺中使用该技术,而是使用DUV光刻机进行四重图案化,结果这导致英特尔在良率方面遇到了重重困难。


回顾历史能看到,2011年英特尔首发了22nm FinFET工艺,远超当时台积电、三星的28nm,技术优势可谓遥遥领先。然而从14nm节点开始,英特尔接连遭受重创。


2014年,英特尔和三星都实现了14nm制程芯片的生产,可到2017年,台积电已经推进到10nm、7nm工艺,英特尔却因为不愿意采用最新的EUV光刻技术,这导致其原计划在2016年大规模量产10nm芯片直到2019年才实现量产,比台积电推出时间晚了两年半,而其7nm芯片更是直至2022年才推出。


实际上,除了没能把握住EUV技术之外,英特尔代工的衰退与其“Tick-Tock”战略也脱不了关系。


英特尔前任CEO保罗·欧德宁对于芯片制造曾提出“Tick-Tock”战略,即在Tick年(工艺年)更新制作工艺,Tock年(架构年)更新微架构,相当于每两年一次工艺制程进步。但同期,为推行“高效管理”“成本节约计划”,英特尔裁员2万人,大量参与下一代芯片工艺和架构研发的工程师被裁撤,导致“Tick-Tock”模式难以持续,14nm芯片延迟一年才推出,10nm芯片更是几番推迟。


英特尔像挤牙膏一样对芯片技术进行微小的年度更新,那些年它一度被大家讥讽为“牙膏厂”。


随着Tick-Tock模式的崩溃,以及错失EUV早期技术窗口,英特尔开始逐渐掉队。


与此同时,台积电和三星从ASML大量采购EUV设备,不断缩小芯片的制程尺寸,提高芯片的效率和性能,大大提升了在晶圆代工领域的竞争力。在先进制程上,英特尔被台积电、三星远远甩在了身后。


更严重的是,生产工艺落后、产品竞争力下滑,不仅影响了英特尔的代工业务,也使其台式机芯片和服务器芯片的市场份额不断被蚕食。


可谓,牵一发而动全身。


二、英特尔自救,前路何在?


因此,痛定思痛后的英特尔,率先对High-NA EUV光刻机展开了攻势,试图追回被拉开的差距。


上面提到,2024年4月,重达150吨的巨大设备被安装在英特尔位于美国俄勒冈州的研究设施里。


这也是在英特尔CEO Pat Gelsinger提出“IDM 2.0”战略后,迅速重新聚焦于尖端制程工艺的提升,提出了四年五个工艺节点的计划,希望在2025年凭借Intel 18A实现对于台积电2nm工艺的追赶和超越。



与此同时,英特尔希望通过率先采用High NA EUV光刻机来实现对于台积电等竞争对手的持续领先。英特尔的目标是在2026至2027年间实现Intel 14A制程技术的量产,并在此基础上进一步提升制程技术。最终在2030年前实现英特尔代工业务实现收支平衡的运营利润率,并成为全球第二大晶圆代工厂。


在目标指引下,英特尔正不断加强代工基础设施建设,计划未来5年投资1000亿美元扩大先进芯片制造能力。同时将投资约300亿欧元在德国马格德堡建设两家半导体工厂。这些投资计划将使英特尔芯片代工能力大幅提升。


然而,战略愿景很美好,但现实却很残酷。


尽管英特尔雄心勃勃,但由于四年五个节点及路线演进、生态构建和产能扩建等巨额的投入,英特尔披露其代工业务去年营收同比下降31.2%至189亿美元,经营亏损70亿美元,同比扩大34.6%。


2024年有可能将是英特尔芯片制造业务经营亏损最严重的一年,今年Q1财报显示,该业务运营亏损25亿美元,几乎是上一季度的两倍;Q2亏损更是达到28.3亿美元,代工亏损额不断扩大。


据研究机构TrendForce集邦咨询数据,2024年第二季度,英特尔并未进入全球晶圆代工厂营收前10名。在过去几年里,英特尔曾经在2023年第三季度短暂上榜,市场份额仅为1%。


这意味着,IFS三年来无法真正托举起英特尔以尖端芯片制造重塑行业地位的目标,同时作为美国本土唯一有能力承担起前沿代工行业的角色,英特尔也无法扛起时代重任。


据心智观察所报道,美国半导体咨询公司D2D Advisory总裁Jay Goldberg也特别指出:“英特尔代工面临的真正挑战,还在于他们的经济模式中必须要拥有更多的客户,以支持不断推进其制造流程所需的研发。必须加大外部客户需求,将收入规模增加一倍,以支持保持在摩尔定律的轨道上继续前进。”


不难看到,英特尔目前已陷入两难境地,业绩持续下滑,2024年甚至由盈转亏,股价暴跌将近60%,市值几度跌破千亿美元,成为标普500指数中表现最差的科技股之一。


面对危机,英特尔在内部信上表示,将进一步分离芯片制造和设计业务,这是该公司解决50年历史上最严重危机之一的一系列新措施的一部分。


根据英特尔此前公布的预测数据,分拆晶圆制造业务后,2023年可以节省30亿美元成本,2025年将节省80亿~100亿美元成本。同时也推迟德国和波兰建厂计划2年;马来西亚建厂会完成,但正式启用时间则视市况与产能利用率而定。


在英特尔继续紧急行动执行上个月宣布的计划的同时,英特尔也在努力谨慎地管理现有的现金,以有意义地改善资产负债表和流动性。其中就包括出售部分Altera的股份,并推动其独立IPO;产品研发策略方面,也规划将简化x86产品组合。这也是英特尔多次公开讨论的计划。


今年8月,英特尔甚至还被曝出正在考虑分拆其产品和代工业务。值得一提的是,在传出或分拆其晶圆业务之后,英特尔股价曾反弹9%以上,可见投资者对其芯片代工业务有多失望。


处在低谷中的英特尔就是美国芯片制造业的一个缩影,成本、技术、资源、IDM身份等,都在制约英特尔野心勃勃的芯片代工计划。但尽管业界也有放弃芯片代工的可能性探讨,尽管芯片代工业务持续的亏损已经让资本市场不满意,但这也是为数不多能拯救英特尔于水火的关键布局。


英特尔没有选择,只有抓住任何的可能性,硬着头皮上。


因此,英特尔需要最尖端的High-NA EUV光刻机作为生产和营销工具,以宣示自身在3nm以下的研发制造实力且尝试壮大客户群,但High-NA EUV光刻机作为新机,又让英特尔不得不冒着设备折旧和量产摊销成本的压力以平息外界质疑。


从行业竞争的持续以及芯片代工“重资产、长周期”的产业属性来看,英特尔还有诸多硬仗要打。尤其是在英特尔开启公司史上最大转型以自救的处境下。


英特尔过去也有过从困境中复苏的经历。1980年代,在日本企业的攻势下,英特尔撤出了DRAM,把经营资源集中于CPU,席卷了个人电脑市场。


正如基辛格所述:“这是英特尔四十多年来最重要的转型。自从内存过渡到微处理器以来,我们还没有尝试过如此重要的事情。我们当时成功了,我们将迎接这一时刻,并在未来几十年内打造更强大的英特尔。”


但英特尔的种种自救,仍需要时间检验。


三、三星电子,陷代工阴霾


今年8月,在“2024年光刻+图案学术会议”上,三星电子表示,为了在与英特尔、台积电等全球半导体竞争对手的“芯片战”中保持竞争力,公司正在积极参与技术开发,最早将在2024年底到2025年第一季度之间引进公司首台High-NA EUV设备“EXE:5000”,并有望在2027年实现该技术的全面商业化。


据悉,该设备可能被放置在位于华城园区的半导体研究所(NRD),预计将用于代工业务,以进一步提升在先进节点领域的竞争优势。


实际上,三星芯片代工在早年占据了绝对优势。2007年乔布斯发布第一代iPhone时,使用的正是从三星采购的ARM架构芯片。后续搭载于iPhone 4、iPhone 4s、iPhone 5、iPhone 5s/5c身上的A4、A5、A6、A7芯片也均由三星代工,那时候还没有台积电什么事。


直到2011年,因为三星自己也从事手机芯片和手机终端研发和销售业务,如此一来就与苹果在智能手机市场上有了竞争关系。双方互相拉扯,直到2018年6月才达成和解。


在这个过程中,苹果也开启了“去三星化”进程。2014年推出的A8芯片,全部转由台积电代工。台积电能顺利从三星手中抢到苹果的订单,一方面是苹果急着寻找可替代的代工商,给台积电制造了很大的机会。另一方面是台积电在20nm工艺上取得重大突破,良品率大幅提升,而三星的20nm工艺突然掉链子,关键问题迟迟无法解决,良品率满足不了苹果的要求。正是这样的天时地利,让台积电成功抱到了苹果这条大腿。


反观三星,在大客户被抢之后,决定不搞20nm,选择直接从28nm跳到14nm,对台积电的16nm形成反超。所以,在2015年的A9芯片上,苹果又重新分给三星一部分订单,于是出现台积电代工和三星代工两种版本。理论上,三星14nm表现应该是优于台积电16nm,但消费者的口碑却完全相反,很多人都担忧买到三星代工的版本。


这次的失利,让三星彻底失去苹果的代工订单,苹果公司之后的芯片均由台积电代工,制程也从2015年的16nm,稳步提升到4nm。


与此同时,高通也险些在三星代工中跌了跟头,骁龙8+Gen1紧急转为台积电4nm代工,才强行挽回了高通的口碑和市场地位。


在芯片代工赛道上,三星具有起步优势,但奈何中期连续多次失利,才让台积电一步步实现反超,直至今日的大幅领先。然而,三星也清楚自己与台积电之间存在技术差距,所以想要对台积电形成反超,就必须拿出更强的“杀手锏”。


于是,三星几乎把追赶台积电的全部希望都押注在3nm工艺上。2023年,三星率先推出3nm制程工艺,采用更加先进的GAA(环绕栅极晶体管)技术,领先于台积电的FinFET技术。


可以说,3nm相当于三星最后的“背水一战”,如果能一举追赶台积电,或许未来有机会形成双雄争霸的局面。


然而从市场进展来看,三星3nm工艺在良率方面面临挑战,这导致了一个很尴尬的局面,即三星的3nm芯片,虽然比台积电先推出,但是成本却比台积电高出很多,性能表现也存在差距。据悉,三星第二代3nm制程工艺良品率不稳定,自家Exynos2500良品率都不足20%,三星Galaxy25系列手机全系搭载骁龙8Gen4处理器,放弃自研Exynos2500版本,原因是体验差异太大。


与台积电差距拉开之后,给三星下订单的客户越来越少。


过去高通先进制程的芯片一直都是三星独家代工,结果在5nm芯片之后,高通也将先进制程的芯片订单交给了台积电;现如今,苹果的A17、A18系列芯片,全部采用台积电的3nm工艺制造;高通的3nm芯片和联发科的天玑9400等也全由台积电代工;连英伟达、AMD、特斯拉的3nm芯片,都是台积电代工,包括现在英特尔的订单也给了台积电。


在芯片制造上,台积电一家拿下了全球60%以上的市场份额,3nm的芯片制造几乎拿下100%的份额,而7nm以下的芯片制造,拿下了90%的份额。第二大晶圆厂三星的市场份额仅为11.5%。


据《朝鲜日报》消息,三星已经将平泽2厂,3厂的4nm,5nm和7nm生产线关闭了30%产能。预计到2024年底,还将继续关闭产能直到50%。这一举措显然是为了应对全球科技巨头如英伟达、AMD及高通等未能给予三星电子大规模订单的现状。


有行业专家强调,一旦设备关闭,恢复正常运营是一个漫长的过程。通常情况下,即使在需求低迷时期,公司也会降低利用率,而不是全面停工。然而,三星近30%的先进工艺设备闲置是前所未有的。


2024年第三季度,三星包括晶圆代工和系统LSI等非内存部门亏损金额超过1万亿韩元。此外,三星3nm制程的良率持续处于低位,也一直没有获得大客户的采用,近期还将美国得州泰勒市先进代工晶圆厂量产时间延后到2026年。


综合来看,这样的差距,让三星在3nm时代想要超越台积电的梦想彻底破灭了。


因此,三星引进High-NA EUV光刻机的消息,意味着其将与英特尔和台积电在下一代光刻技术上展开更为激烈的竞争。


三星计划在2025年量产2nm制程,并逐步扩展到其他应用领域。比如,2025年首先用于行动领域,2026年扩展到HPC应用,2027年再扩展至汽车领域。三星的2nm制程节点采用了优化的背面供电网络技术,以降低供电电路对信号电路的干扰。


这一发展标志着三星首次涉足High NA EUV技术。此前,三星电子曾与IMEC合作进行电路处理研究。三星计划利用自己的设备加速先进节点的开发,并设定了到2027年实现1.4nm工艺商业化的目标,这可能为1nm生产铺平道路。


此外,为了实现全面商业化,三星还正在积极构建相关生态系统。


据悉,三星电子已购买了雷射技术公司的High-NA EUV掩膜检查设备"Actis(ACTIS)A300"。预计在三星电子内部完成ASML的EXE:5000安装后,将从明年上半年开始正式引进。同时与电子设计自动化(EDA)公司合作设计新型光罩,包括用于High-NA EUV的非直线(Curvilinear)掩膜电路绘制方法,以提高晶圆上印刷电路的清晰度。此次合作涉及半导体EDA工具全球领导者Synopsys等公司。


除了ASML、雷射技术公司、Synopsys之外,三星电子预计还会与JSR等光刻胶公司、将光刻胶涂在晶圆上的跟踪设备"Number One"东京电子等多家公司合作,为High-NA时代到来做准备。据悉,三星电子正通过这样的生态系统建设工作,准备在2027年正式商用High-NA。


三星电子的晶圆代工业务正站在一个关键的十字路口,其生死存亡,似乎全系于2nm芯片制程技术的量产之上。这不仅是技术上的飞跃,更是三星晶圆代工业务能否重获新生的关键。


然而通往成功的道路从来都不是一帆风顺的。三星在推进其技术蓝图的过程中,不得不面对一系列严峻的挑战:


首先是技术层面的难题,先进制程的良率问题一直是悬在半导体厂商头上的达摩克利斯之剑。三星的3纳米制程就因良率低迷、可靠性存疑而未能达到量产标准,这无疑给其晶圆代工业务蒙上了一层阴影。


更糟糕的是,市场的反应也并未如三星所愿。尽管三星努力提升技术实力,但在客户心中,其晶圆代工业务的可靠性和竞争力仍显不足。面对台积电等强劲对手,三星在争取高端客户方面显得力不从心。这种市场困境,进一步加剧了三星的财务压力。据估算,三星晶圆代工业务在第三季度恐将亏损数千亿韩元,这是对三星管理层的一次重大考验。


面对内忧外患,三星高层不得不做出一系列艰难的决定。


根据研究公司Statista的数据,尽管三星多年来一直努力挑战台积电,但三星在代工制造市场的份额在过去五年里下降了8个百分点,2024年第二季度,三星占据全球代工市场份额的11.5%,而台积电占据62.3%的市场份额。


三星市场份额的下降凸显了其在掌握先进芯片制造技术方面面临的技术挑战,在代工业务上投资过多,既没有获得足够的客户,也没有稳定生产工艺,这进一步导致了三星目前的危机。


综合来看,半导体行业本身是技术快速迭代与市场变幻莫测的领域,三星必须保持足够的敏锐度,以应对未来的变化。如何在快速变化的市场中找到适合自身发展的道路,是三星当前亟待解决的问题。


四、台积电“有条不紊”,赢下“谈判游戏”


作为半导体行业的领导者,台积电在过去的30多年中立下了赫赫战功。过去多年来,在面对三星和英特尔带来的巨大挑战和压力时,台积电审时度势并采取有效的措施,成为了世界第一大芯片代工企业。


如今,即使行业头部半导体企业纷纷争夺High-NA EUV设备,台积电似乎并不急于加入这一行列。


此前,谈到何时导入High-NA EUV设备,台积电资深副总暨副共同营运长张晓强接受外界采访时透露,台积电胸有成竹,不会因为对手们抢先添购设备而盲目扩大采购,仍采稳扎稳打方式布局先进制程,迎接挑战。


然而,近期有消息报道,台积电预计将于今年年底从ASML接收首批全球最先进的芯片制造设备——高数值孔径极紫外(High NA EUV)光刻机。这一消息标志着台积电在半导体制造领域再次迈出了重要一步。


有趣的是,台积电前期以成本为由,迟迟不肯接受High NA EUV。早些时候,台积电CEO魏哲家缺席“台积电技术研讨会2024”,而是前往荷兰埃因霍温的ASML总部洽谈设备。


如今看来,这有点像台积电的谈判游戏,也许是在与ASML争取更好的条件。


传闻魏哲家亲自与ASML谈判并达成了一项协议,通过购买新设备和出售旧型号相结合的方式,将整体价格降低了近20%。ASML同意以折扣价向台积电出售High-NA EUV设备主要因为台积电是其超级VIP客户,ASML给予了很大的让步。这一让步包括全力协助台积电进机、调校与技术支援等,以加速上线时间点。


因此,台积电的态度也发生了戏剧性的转变,由原先对新款High NA EUV光刻机价格的犹豫,转为积极寻求合作。


据悉,台积电则预计将在本季度在其位于中国台湾新竹总部附近的研发中心安装新的High NA EUV光刻机。短期内,台积电计划将High NA EUV光刻机主要用于研发,以开发客户推动创新所需的相关基础设施和模式解决方案。


根据ASML的路线图,第一代的High-NA EUV光刻机TWINSCAN EXE:5000或许主要是被晶圆制造商用于相关实验与测试,以便公司更好地了解High-NA EUV设备的使用,获得宝贵经验。实际量产将会依赖于2024年底出货的TWINSCAN EXE:5200。



台积电即将推出的N2(2纳米级)和A16(1.6纳米级)工艺技术将完全依赖于传统的EUV设备,这些设备的光学元件具有0.33 NA。业界预计,台积电最早可能在2028年或更晚的A14(1.4纳米级)工艺技术中采用0.55 NA EUV工具,尽管目前公司尚未对此进行官方确认。


与竞争对手相比,台积电可以通过持续的生产实践积累宝贵的经验数据与优化工艺,从而难以构建起“订单驱动-技术迭代-再获订单”的良性循环体系。换言之,台积电有着极为庞大的优质客户群协助他们调试各种设备bug,这恰恰是三星和英特尔所缺少的。


1. 台积电布局策略:无宝不落


笔者此前曾提到,从三巨头布局策略和方式来看,台积电往往被认为是一个保守技术开发者,其倾向于确保新技术的成熟和可靠性,然后再进行部署,而不是急于将新技术推向市场。


从实际的市场表现来看,台积电此举可以降低技术失败的风险,提高其芯片的产量和质量,从而确保客户的满意度。


例如,三星在2018年开始在其7nm工艺中使用EUV光刻机,然而台积电选择等待。直到EUV工具的稳定性和成熟性得到确认,以及相关问题得到解决或至少得到确定,才在2019年的N7+工艺中开始使用EUV。


此后,在FinFET向GAA工艺的过渡上,台积电依旧重操这一模式。凭借工艺领先性和生产良率上的技术优势和积累完全有实力与采用GAA技术架构的三星抗衡。


在英特尔大力押注的BSPDN背面供电技术上,台积电依旧不紧不慢,计划将在2026年底才开始大规模生产的N2P上加入。


这种谨慎的方法有助于台积电确保其制程技术的稳定性和可预测性,从而提供高质量的芯片给其客户。


但从先进封装领域来看,台积电则一改常态,积极布局率先落地,在先进制程与先进封装的组合拳下,为其带来了新的增长浪潮。


在这张弛有度的策略下,充分凸显着台积电的战略哲学和独到眼光。在其看准的蓝海赛道,台积电始终敢为人先,无论是十年前率先试产16nm FinFET制程技术超越英特尔,还是五年前部署先进封装收获如今的AI红利,台积电都精彩演绎了所谓凤凰无宝不落。


而在其保持较大优势的先进制程领域,纵然面对三星和英特尔的步步紧逼,台积电没有选择盲目激进,反而采取了先观察再跟随的策略,在做好充分的准备和规划后“亦步亦趋”,凭借自身强大的产能、良率和客户基础的基本盘优势,维持不败之地。


五、SK海力士发力High NA EUV,押宝HBM


此外,在存储领域,SK海力士的首台High NA EUV光刻机“EXE:5200”则有望于2026年引入,旨在支持其先进DRAM产品的量产。这一举措进一步彰显了半导体行业对于先进制程技术的持续追求和投入。


2023年,SK海力士就曾单独组建了一个团队,专门开发High-NA EUV技术。


SK海力士作为HBM领域巨头,正不断加大对High-NA EUV技术开发的内部投入,积极扩大相关研发团队。尽管关于设备安装的具体晶圆厂位置及额外投资方向等信息尚未公开,但业界普遍预期,该技术将迅速应用于0a(个位数纳米)DRAM的规模化生产,以进一步提升产品竞争力。


写在最后


7nm以下的世界是另类冒险家的乐园,台积电,三星和英特尔的竞合关系变得愈发微妙。


根据光刻机之“瑞利公式”,光刻工艺的提升在过去几十年来一直在多维度全面出击,即不断优化曝光波长、数值孔径以及工艺因子。但目前曝光波长的缩短、数值孔径(NA)的增加都已经逼近了物理和成本综合考量的极限。


如今距离摩尔定律的极限越来越近,行业几乎走到了隧道尽头,2nm及接下来几代工艺节点将会是芯片巨头抢滩的关键。


在全球范围内,台积电、英特尔和三星等半导体巨头之间的竞争正在升温,它们竞相获得2nm以下工艺的High NA EUV设备。英特尔于2023年12月率先获得该设备,台积电于2024年第三季度紧随其后。尽管三星的订单来得晚,但实现稳定的生产可能是决定行业领先地位的关键因素。


但芯片代工的竞争,不仅仅是技术的竞争,更是客户、品牌、良率、产能等各方面的综合竞争。不知道,英特尔和三星能否在新市场的黎明期抓住重新崛起的机会。如果失败,台积电将继续独占鳌头。


本文来自微信公众号:半导体行业观察 (ID:icbank),作者:L晨光

本内容为作者独立观点,不代表虎嗅立场。未经允许不得转载,授权事宜请联系hezuo@huxiu.com
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